This application claims priority to Korean Patent Application No. 2001-2951, filed on Jan. 18, 2001, which is commonly owned and incorporated herein by reference.
1. Technical Field
The present invention generally relates to a semiconductor memory device comprising control pads and I/O (input/output) pads, and more particularly, to a semiconductor memory device comprising control pads and input/output I/O pads that are arranged on a memory chip to thereby reduce the length of data paths for reading/writing data from/in a cell array, and to a method for driving the semiconductor memory device.
2. Description of Related Art
A semiconductor memory device comprises data paths for reading/writing data from/to a cell array. The data paths extend from control pads to I/O pads through a memory cell within a memory chip. The length of a data path is determined by the arrangement of chip pads, e.g., control pads or I/O pads).
FIG. 1 is a diagram illustrating an arrangement of control pads and I/O pads in a conventional semiconductor memory device. In FIG. 1, a conventional semiconductor memory device comprises a plurality of memory banks BA11-BA14 arranged at the central region of a memory chip 10, each of the memory banks comprising a plurality of memory cells, and a plurality of control pads CPAD1 and a plurality of I/O pads IOPAD1 sequentially arranged in a region between adjacent memory banks of the memory chip 10.
The conventional semiconductor memory device can only read/write the data stored/to be stored in one of the memory banks BA11-BA14 from/in the corresponding memory bank. For example, the data stored (or the data to be stored) in the first memory bank BA11 can only be read/written from/in the first memory bank BA11. Similarly, the data stored/to be stored the second, third, and fourth memory banks BA12, BA13, BA14 can only read/written from/in the second, third, and fourth memory bank BA12, BA13, BA14, respectively.
The memory banks BA11-BA14 commonly share the plurality of control pads CPAD1 and the plurality of I/O pads IOPAD1 for controlling the reading/writing operations of the semiconductor memory device. That is, the data stored/to be stored in one of the memory banks BA11-BA14 is read/written in the corresponding memory bank through all the control pads CPAD1 and the I/O pads IOPAD1. Accordingly, the conventional semiconductor memory device has a disadvantage in that data paths become longer.
Further, since the control pads CPAD1 and the I/O pads IOPAD1 arranged in the region between adjacent memory banks of the memory chip 10, another disadvantage is that the data path for reading/writing data in a given memory cell become longer than the data path in another memory cell.
For example, when the data stored in memory cell CE1 of the first memory bank BA11 is read from the first memory bank BA11, the data is supplied from the memory cell CE1 to the I/O pads IOPAD1 through a first path DP11. And then, the signal for reading data is applied from the control pad CPAD1 to the memory cell CE1 of the first memory bank BA11 though a second path DP12. In contrast, when the data to be stored in the memory cell CE1 of the first memory bank BA11 is written in the first memory bank BA11, the data is supplied from the I/O pad IOPAD1 to the memory cell CE1 through the first path DP11. Then, the signal for writing data is applied from the control pad CPAD1 to the memory cell CE1 of the first memory bank BA11 through the second path DP12. Accordingly, the length of the data path for reading or writing data is the sum of lengths of the first path DP11 and the second path DP12. Thus, a conventional semiconductor memory device having an architecture as shown in FIG. 1 have long data paths.
Furthermore, the conventional semiconductor memory device of FIG. 1 has a disadvantage in that the length of the data path in the chip becomes longer as the memory capacity increases. The data path in the inside of the chip is the distance from the control pad CPAD1 to the I/O pad IOPAD1 through a memory cell.
Another conventional semiconductor memory device design comprises an arrangement of I/O pads and control pads at the edge portion of a memory chip in which memory banks are located at the central portion of the memory chip. However, such a pad arrangement also has a disadvantage that the data path is long.
To overcome disadvantages of conventional pad arrangements in semiconductor memory devices, it is object of the present invention to provide a semiconductor memory device capable of reducing the data paths for writing/reading data.
It is another object of the present invention to provide a semiconductor memory device comprising control pads and I/O pads separately arranged from each other, thereby reducing the data paths for reading/writing data.
It is another object of the present invention to provide a semiconductor memory device capable of reducing the data paths for reading/writing data and having a uniform length of the data path irrespective of location of a written/read memory cell.
It is further object of the present invention to provide a method for driving a semiconductor memory device capable of reducing the data path for reading/writing data in the semiconductor memory device.
In one aspect of the present invention, a semiconductor memory device, comprises:
a plurality of memory banks; and
a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the memory banks, wherein the plurality of control pads and I/O pads are disposed in a region between adjacent memory banks and in a peripheral region surrounding the memory banks.
In another aspect of the present invention, a semiconductor memory device comprises:
a plurality of memory banks arranged at a cell region of a memory chip; and
a plurality of control pads and a plurality of I/O (input/output) pads, separately arranged from each other at the memory chip, for reading data from and writing data in the memory banks, wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks of the memory chip and the plurality of I/O pads are dispersed in a periphery region surrounding the memory banks.
In yet another aspect of the present invention, a semiconductor memory device comprises:
a plurality of memory banks arranged at a cell region of a memory chip; and
a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the plurality of memory banks, wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks and are commonly shared by the plurality of memory banks, and wherein a predetermined number of I/O pads of the plurality of I/O pads are arranged in a periphery region surrounding the memory banks and the plurality of I/O pads are commonly shared by the plurality of memory banks.
In another aspect of the present invention, a semiconductor memory device comprises:
a plurality of memory banks arranged at a cell region of a memory chip, each of the plurality of memory banks comprising a plurality of bank areas;
a plurality of control pads that are sequentially arranged in a region between adjacent memory banks and are commonly shared by the memory banks; and
a plurality of I/O pads that are arranged in a peripheral region surrounding the memory banks and are commonly shared by memory banks.
In yet another aspect of the present invention, a semiconductor memory device comprises:
a plurality of memory banks arranged at a cell region of a memory chip; and
a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the memory banks,
wherein each of the plurality of memory banks comprises a plurality of bank areas, wherein the number of bank areas corresponds to the number of the plurality of memory banks and the data corresponding to one of the plurality of bank areas is read from or written in the corresponding bank area of each of the memory banks,
wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks and are commonly shared by the plurality of memory banks,
wherein the plurality of I/O pads are arranged in a peripheral region surrounding the memory banks and are commonly shared by the plurality of memory banks, and
wherein a predetermined number of I/O pads are allocated to the outer potion of each of the memory banks.
In another aspect of the present invention, a method is provided for driving data in a semiconductor memory device comprising a plurality of memory banks arranged at a cell region of a memory chip, each of the memory banks comprising a plurality of bank areas in which the number of bank areas corresponds to the number of the memory banks, a plurality of control pads sequentially arranged in a region between adjacent memory banks of the memory chip, and a plurality of I/O pads arranged in a peripheral region surrounding the memory banks, in which a predetermined number of I/O pads are allocated to each memory bank and are disposed near the corresponding memory bank in the peripheral region surrounding the memory banks. The method comprising the steps of:
writing data to be stored in a bank area of a memory bank through the plurality of control pads and the predetermined number of I/O pads allocated to the corresponding memory bank; and
reading data stored in a bank area of a memory bank through the plurality of control pads and the predetermined number of I/O pads allocated to the corresponding memory bank.
These and other aspects, features and advantages of the present invention will be described and become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.